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pseudo differential, 555 ksps 12-bit adc in an 8-lead sot-23 ad7453 rev. b in fo rmation furn ished by an alog d e v i c e s is believed to be accurate and reliable. how e ver, n o resp on sibili ty is assume d b y a n alog de vices fo r its use, nor for an y i n fri n geme nt s of p a t e nt s or ot h e r ri ght s o f th ird parties th at may result fro m its use . s p ecificatio n s subj ec t to ch an g e witho u t n o tice. no licen s e is g r an te d by implicati o n or ot herwi s e u n der a n y p a t e nt or p a t e nt ri ghts of analog de v i ces. trademarks an d registered tra d ema r ks are the prop erty o f their respective ow ners. one technolog y way, p.o . box 9106, norwood, ma 02062-9106, u.s.a. t e l: 781. 329. 4 700 www.analog.com fax: 781. 326. 87 03 ? 2004 analog de vices, i n c. al l r i ght s r e ser v ed . features specified for v dd of 2.7 v to 5. 25 v low power at max throughput rate: 3.3 mw max at 555 ksps with v dd = 3 v 7.25 mw max a t 555 ksps wit h v dd = 5 v pseudo differe ntial analog in put wide input bandwidth: 70 db sinad at 100 khz input frequency flexible power/serial clock speed managem e nt n o pipeline delays high speed s e r i al interface: spi?/qspi?/microwire?/dsp compatible power-down mode: 1 a m a x 8-lea d sot-23 package applic ati o ns transducer int e rface battery-powered systems data acq u isitio n systems portable instrumentation general description the ad7453 1 is a 12-b i t, hig h sp eed , lo w p o w e r , s u cces s i v e ap p r ox i m at i o n ( s a r ) a n a l o g - t o - d i g i t a l c o n v e r t e r t h at f e a t u r e s a ps eudo dif f er en t i al a n alog i n p u t. this p a r t o p er a t es f r o m a sin g le 2.7 v t o 5 . 25 v p o w e r s u p p l y a n d f e a t ur es thr o ug h p u t ra t e s u p t o 555 ks ps. t h e p a r t c o n t a i ns a l o w noi s e, w i d e b a nd w i d t h , d i f f e r e n t i a l t r ack-and- h o ld a m plif ier (t /h) t h a t c a n hand le in p u t f r e q ue n- cies u p t o 3.5 mh z. the r e f e r e nce v o l t a g e f o r the ad7453 is a p pl i e d e x te r n a l ly to t h e v ref p i n an d can ra n g e f r o m 100 mv to v dd , dep e n d i n g o n t h e p o w e r sup p ly a nd w h a t sui t s t h e ap p l i c at i o n . the con v ersio n p r o c es s an d da t a acq u isi t ion a r e co n t r o l l e d usin g cs a n d t h e s e ri al c l oc k , allo w i n g th e devi ce t o i n t e rfa c e w i t h m i c r opro c e ss or s or d s p s . t h e i n put s i g n a l s are s a m p l e d o n th e fal l in g edge o f cs ; t h e co n v ersio n is a l s o ini t i a te d a t t h is po i n t . the sar a r chi t e c t u r e o f t h is p a r t en s u r e s t h a t t h er e a r e n o p i p e lin e de l a ys. the ad7453 us es ad van c e d des i g n t e chniq u es to achie v e ve r y low p o we r diss i p a t ion . func tio n a l block di agram v ref t/h control logic 12-bit successive adc gnd sclk sdata cs v dd ad7453 v in+ v in ? approximation 03155-a - 001 fi g u r e 1 . product highlights 1. o p era t ion wi th 2.7 v t o 5.25 v p o w e r s u p p l ies. 2. h i g h thr o ug h p u t wi th l o w p o w e r c o n s um p t io n. w i th a 3 v s u p p l y , th e ad7453 o f f e rs 3.3 mw max p o w e r co n s um p t io n f o r a 555 ks ps thro ug h p u t r a t e . 3. p s eudo dif f er en t i al analog i n pu t. 4. flexi b le p o w e r/s e r i al c l o c k s p e e d m a na ge m e n t . th e c o n v e r s i on r a te i s de te r m i n e d by t h e s e r i a l cl o c k , a l l o w i ng t h e p o w e r t o b e r e d u ce d as t h e c o n v ersio n t i m e is r e d u ce d th r o ugh th e se rial c l oc k s p e e d in cr ea s e . t h i s pa r t also fe a t ur es a sh u t do wn m o de t o maximize p o w e r ef f i cien c y a t lo w e r thr o ugh p u t ra t e s. 5. v a r i abl e v o lt age r e fe re nc e in put . 6. no p i p e l i n e d e l a y . 7. a c c u ra t e con t r o l o f t h e s a m p ling in st an t v i a a cs in p u t and onc e - o f f c o n v e r s i on c o n t ro l. 8. en o b > 10 b i ts t y p i cal l y wi th 500 mv ref e r e n c e. 1 protected by u.s. patent number 6,681,332.
ad7453 rev. b | page 2 of 20 table of contents specifications..................................................................................... 3 timing specifications .................................................................. 5 absolute maximum ratings............................................................ 6 esd caution.................................................................................. 6 pin configuration and function descriptions............................. 7 terminology ...................................................................................... 8 ad7453Ctypical performance characteristics ............................ 9 circuit information ........................................................................ 11 converter operation.................................................................. 11 adc transfer function............................................................. 11 typical connection diagram ................................................... 12 the analog input........................................................................ 12 digital inputs .............................................................................. 13 reference ..................................................................................... 13 serial interface ............................................................................ 13 modes of operation ....................................................................... 15 normal mode.............................................................................. 15 power-down mode .................................................................... 15 power-up time .......................................................................... 16 power vs. throughput rate....................................................... 17 microprocessor and dsp interfacing ...................................... 17 application hints ....................................................................... 19 evaluating the ad7453s performance .................................... 19 outline dimensions ....................................................................... 20 ordering guide .......................................................................... 20 revision history 2/04data sheet changed from rev. a to rev. b added patent note ....................................................................... 1 1/04data sheet changed from rev. 0 to rev. a updated format..............................................................universal changes to general description ................................................ 1 changes to specifications ............................................................ 3 changes to timing specifications .............................................. 5 changes to table 4........................................................................ 7 replaced figures 11, 12, 13........................................................ 10 changes to typical connection diagram section ................. 12 change to figure 18 ................................................................... 12 changes to reference section................................................... 13 changes to timing example 1.................................................. 14 8/03rev. 0: initial version
ad7453 rev. b | page 3 of 20 specifications v dd = 2.7 v to 5.25 v, f sclk = 10 mhz, f s = 555 ksps, v ref = 2.5 v, f in = 100 khz, t a = t min to t max , unless otherwise noted table 1. parameter test conditions/comments a version 1 b version 1 unit dynamic performance f in = 100 khz signal to noise ratio (snr) 2 v dd = 2.7 v to 5.25 v 70 70 db min signal to (noise + distortion) (sinad) 2 v dd = 2.7 v to 3.6 v 69 69 db min v dd = 4.75 v to 5.25 v 70 70 db min total harmonic distortion (thd) 2 v dd = 2.7 v to 3.6 v; C78 db typ C73 C73 db max v dd = 4.75 v to 5.25 v; C80 db typ C75 C75 db max peak harmonic or spurious noise 2 v dd = 2.7 v to 3.6 v; C80 db typ C73 C73 db max v dd = 4.75 v to 5.25 v; C82 db typ C75 C75 db max intermodulation distortion (imd) 2 fa = 90 khz; fb = 110 khz second-order terms C80 C80 db typ third-order terms C80 C80 db typ aperture delay 2 5 5 ns typ aperture jitter 2 50 50 ps typ full-power bandwidth 2 , 3 @ C3 db 20 20 mhz typ @ C0.1 db 2.5 2.5 mhz typ dc accuracy resolution 12 12 bits integral nonlinearity (inl) 2 1.5 1 lsb max differential nonlinearity (dnl) 2 guaranteed no missed codes to 12 bits 0.95 0.95 lsb max offset error 2 3.5 3.5 lsb max gain error 2 3 3 lsb max analog input full-scale input span v in+ C v inC v ref v ref v absolute input voltage v in+ v ref v ref v v inC 4 v dd = 2.7 v to 3.6 v C0.1 to +0.4 C0.1 to +0.4 v v dd = 4.75 v to 5.25 v C0.1 to +1.5 C0.1 to +1.5 v dc leakage current 1 1 a max input capacitance when in track/hold 30/10 30/10 pf typ reference input v ref input voltage 1% tolerance for specified performance 2.5 5 2.5 5 v dc leakage current 1 1 a max v ref input capacitance when in track/hold 10/30 10/30 pf typ logic inputs input high voltage, v inh 2.4 2.4 v min input low voltage, v inl 0.8 0.8 v max input current, i in typically 10 na, v in = 0 v or v dd 1 1 a max input capacitance, c in 6 10 10 pf max logic outputs output high voltage, v oh v dd = 4.75 v to 5.25 v, i source = 200 a 2.8 2.8 v min v dd = 2.7 v to 3.6 v, i source = 200 a 2.4 2.4 v min output low voltage, v ol i sink = 200 a 0.4 0.4 v max floating-state leakage current 1 1 a max floating-state output capacitance 6 10 10 pf max output coding straig ht (natural) binary
ad7453 rev. b | page 4 of 20 parameter test conditions/comments a version 1 b version 1 unit conversion rate conversion time 1.6 s with a 10 mhz sclk 16 16 sclk cycles track-and-hold acquisition time 2 sine wave input 250 250 ns max full-scale step input 290 290 ns max throughput rate 555 555 ksps max power requirements v dd 2.7/5.25 2.7/5.25 v min/max i dd 7 , 8 normal mode (static) sclk on or off 0.5 0.5 ma typ normal mode (operational) v dd = 4.75 v to 5.25 v 1.5 1.5 ma max v dd = 2.7 v to 3.6 v 1.2 1.2 ma max full power-down mode sclk on or off 1 1 a max power dissipation normal mode (operational) v dd = 5 v; 1.55 mw typ for 100 ksps 7 7.25 7.25 mw max v dd = 3 v; 0.64 mw typ for 100 ksps 7 3.3 3.3 mw max full power-down mode v dd = 5 v; sclk on or off 5 5 w max v dd = 3 v; sclk on or off 3 3 w max 1 temperature ranges as follows: a, b versions: C40c to +85c. 2 see section. terminology 3 analog inputs with slew rates exceeding 27 v/s (full-scale input sine wave > 3.5 mhz) within the acquisition time may cause a n incorrect result to be returned by the converter. 4 a small dc input is applied to v inC to provide a pseudo ground for v in+ . 5 the ad7453 is functional with a refere nce input in the range 100 mv to v dd . 6 guaranteed by characterization. 7 see section. power vs. throughput rate 8 measured with a full-scale dc input.
ad7453 r e v. b | pa ge 5 o f 2 0 timing spe c ific ations g u a r an t e ed b y c h a r ac t e r i za tio n . al l in p u t sig n a l s a r e s p ecif ied wi t h tr = tf = 5 n s (10% t o 90% o f v dd ) a n d t i me d f r o m a vol t age lev e l o f 1.6 v . s e e f i gur e 2 and t h e s e r i a l i n te r f ace s e c t io n. v dd = 2.7 v t o 5.25 v , f sc l k = 10 mh z, f s = 555 ks ps, v ref = 2.5 v , t a = t min to t max , u n l e ss ot he r w i s e note d. table 2. parameter limit at t min , t ma x unit description f sclk 1 10 khz min 10 mhz max t con v ert 16 t sclk t sclk = 1/f sclk 1.6 s max t qu iet 60 ns min minimum quiet time between the end of a se rial read and the next falling edge of cs t 1 10 ns min minimum cs pulse wid t h t 2 10 ns min cs falling edge to sclk falling edge setup time t 3 2 20 ns max delay from cs falling edge until s d ata three-state disabled t 4 2 40 ns max data access time after sclk falling edge t 5 0.4 t sclk ns min sclk high pulse width t 6 0.4 t sclk ns min sclk low pulse width t 7 10 ns min sclk edge to da ta valid hold time t 8 3 10 ns min sclk falling edge to sdata three-state enabled 35 ns max sclk falling edge to sdata three-state enabled t power - up 4 1 s max power-up time from full power-down t 3 t 2 t 4 t 7 t 8 t 6 t 1 t 5 t quiet t convert cs sclk sdat a 4 leading zeros three-state 12 3 4 5 1 3 1 4 1 5 1 6 0 0 0 0 db11 db10 db2 db1 db0 b 03155-a - 002 f i g u re 2. a d 74 53 s e ri al int e r f ace ti mi ng d i ag r a m 1 mark/ s pace ratio for the sc lk input is 40/60 to 60/40. 2 mea s ure d with the loa d circuit o f a n d d e f i ne d as the time re quire d fo r the o u tput to cro s s 0.8 v or 2.4 v wi th v figu re 3 f i g ure 3. dd = 5 v, and th e time requ ired f o r an output to cross 0.4 v or 2.0 v for v dd = 3 v . 3 t 8 i s d e ri ved f r om t h e m e a s ur ed t i m e t a ken by t h e da t a o u t p ut s t o ch a n ge 0. 5 v wh en loa d ed wi t h t h e ci rcui t o f th e m e a s ured numbe r i s the n extrapo l ate d back to re mo ve the e f f e cts of charging o r d i s c harging the 25 pf capacito r. this me ans that the ti me , t 8 , quoted in the timing characteri s t ics is the true bus rel i nquis h time of the part and is in d e pe nde nt o f the bus lo ad ing. 4 se e powe r- up ti m e s e ct i o n .
ad7453 r e v. b | pa ge 6 o f 2 0 absolute maximum ratings t a = 2 5 c , u n l e ss ot he r w i s e not e d. table 3. p a r a m e t e r r a t i n g v dd to gnd C0.3 v to +7 v v in+ to gnd C0.3 v to v dd + 0.3 v v inC to gnd C0.3 v to v dd + 0.3 v digital input voltage to gnd C0.3 v to +7 v digital output v o ltage to gnd C0.3 v to v dd + 0.3 v v ref to gnd C0.3 v to v dd + 0.3 v input current to any pin except supplies 1 10 ma operating tem p erature range commercia l (a, b version) C40c to +85c storage temperature range C65c to +85c junction tempe r ature 150c ja thermal impedance 211.5c/w (sot-23) jc thermal impedance 91.99c/w (sot-23) lead temperature, soldering vapor phase (60 secs) 215c infrared (15 secs) 220c e s d 1 k v s t r e s s es a b o v e t h os e lis t e d u n de r a b s o l u t e m a xi m u m r a t i n g s ma y c a us e p e r m a n en t dama ge t o t h e de vice . this is a s t r e s s ra t i n g onl y ; f u n c t i o n al o p era t ion o f t h e de vice a t t h es e o r an y o t h e r con d i t io ns a b o v e t h os e list e d i n t h e o p era t io nal s e c t io n s o f t h is sp e c if ic a t io n is n o t i m pli e d . e x p o sur e t o a b s o l u t e max i m u m ra t i ng co ndi t i on s fo r ex ten d e d p e r i o d s ma y a f fe c t de vice r e l i ab i l i t y . 1 transient currents of up to 100 ma wi ll not cau s e scr latch-up. 1.6ma i ol 200 ai oh 1.6v to output pin c l 25pf 03155-a - 003 f i gure 3 . l o a d cir c ui t fo r di g i ta l o u tput t i m i ng sp eci f ic ati o ns esd caution esd (electrostatic discharge) sensitive device. ele c tros tatic charg e s as high as 4000 v readily accumulate on the human body and test eq uipment and can discharge wi thout detection. although this product features proprietary esd protection circu i try, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. theref ore, prop er esd precautions a r e recommended to avoid perform a nce degradation or l o ss of functiona l ity.
ad7453 r e v. b | pa ge 7 o f 2 0 pin conf iguration and fu nction descriptions v dd 1 sclk 2 sdata 3 cs 4 v ref v in+ v in? gnd 8 7 6 5 03155-a-004 ad7453 top view (not to scale) f i gure 4. pin f u nc tion d e sc riptions ta ble 4. pi n f u nct i on d e s c ri pt i o ns nemonic function v ref reference input for the ad7453. an extern al refe rence in the range 100 mv to v dd must be applie d to this input. the specified reference input is 2.5 v. t h is pin should be deco up led to gnd w i th a capacitor of at least 0.1 f. v in+ noninverting analog input. v inC inverting input. this pin sets th e ground reference point for the v in+ input. connect to ground or to a dc offset to provide a pseudo ground. gnd analog ground. ground reference point for all circuitry on th e a d 7453. all analog input signa ls and any external reference signal should be referred to this gnd voltage. cs chip select. acti ve low logic input. this input pr ovides the dual function of initiating a conver si on on the ad7453 and framing the serial data transfer. sdata serial data. logi c output. the co nversion re sult from the ad7453 is provided on this output as a serial data stream. the bits are clocked out on the falling ed ge of the sclk i n put. the data s t ream of the ad 7453 consists of four leading zeros followed by the 12 bits of conversi on data that are provi d ed msb first. t h e output coding is straight (natural) binary. sclk serial clock. log i c input. sclk provides th e serial clock for accessing data from the part. t h is cloc k input is als o used as th e clock source for the conversi on proces s. v dd power supply input. v dd is 2.7 v to 5.25 v. this s u pply should be deco upled to gnd with a 0.1 f capacitor and a 10 f tantalum capacitor.
ad7453 r e v. b | pa ge 8 o f 2 0 terminology signal-to-(noise + distortion) ratio t h e me a s u r e d r a t i o of s i g n a l to ( n oi s e + d i stor t i on ) a t t h e o u t p ut o f t h e a d c. th e sig n al i s t h e r m s am pli t ude o f t h e f u n- d a m e n t al . n o i s e i s th e s u m o f all n o n f un d a m e n t al si gn als u p t o half th e s a m p ling f r e q uen c y (f s / 2 ), excl udin g dc. the ra t i o is dep e n d en t on t h e n u m b er o f q u a n t i za tion levels in the dig i tiza- ti o n p r oce s s; t h e m o r e lev e l s, th e sm alle r th e q u a n tiz a ti o n n o i s e . t h e t h e o re t i c a l s i g n a l - t o - ( n oi s e + d i stor t i on ) r a t i o f o r an i d e a l n- b i t con v er t e r wi t h a si ne w a ve in p u t is g i v e n b y sig n al - to -( no i s e + d i s t or t i on ) = (6.02 n + 1.76) db th us, f o r a 12-b i t con v er t e r , this is 74 db . total harmoni c distortion (thd) t o t a l h a r m on i c d i stor t i on i s t h e r a t i o of t h e r m s su m of ha r m o n ics t o the f u ndam e n t al . f o r th e ad7453 , i t is def i n e d as 1 2 6 2 5 2 4 2 3 2 2 v v v v v v thd + + + + = log 20 ) db ( w h er e v 1 i s th e rm s a m p l i t ud e o f th e fun d a m en tal a n d v 2 , v 3 , v 4 , v 5 , a n d v 6 a r e t h e r m s am pli t udes o f t h e s e c o nd t o t h e sixt h ha r m o n ics. peak harmoni c or spurious noise p e a k ha r m o n ic o r sp ur io us n o is e is def i ne d as t h e r a t i o o f t h e r m s val u e o f t h e n e xt la rg es t com p on e n t i n t h e ad c o u t p ut sp e c t r u m ( u p to f s /2 an d excl udi n g dc) t o t h e r m s val u e o f t h e f u ndam e n t a l . n o r m a l ly , t h e va lue o f t h is sp e c if ica t ion is de t e r - mi n e d b y t h e l a rgest ha r m o n ic in t h e sp e c t r um , b u t fo r ad cs w h er e t h e ha r m o n ics a r e b u r i e d in t h e n o is e f l o o r , i t is a n o i s e peak . intermodulati o n distortion w i t h in p u ts co nsis tin g o f sine wa v e s a t tw o f r eq uen c ies, fa and fb , a n y a c t i v e de v i ce wi th n o nlin ea ri ti e s cr e a t e s d i s t o r ti o n p r o d uc ts a t t h e sum and dif f er en ce f r e q ue n c ies o f mfa nfb wher e m, n = 0, 1, 2, 3, a n d s o on. i n ter m o d u l a t io n dist o r tio n t e r m s a r e th ose f o r whic h n e i t her m n o r n a r e e q ual t o zer o . f o r ex a m ple, t h e s e c o nd-o r der ter m s in cl ud e (fa + f b ) a nd (fa ? fb), while t h e thir d-o r der t e r m s in c l ude (2fa + fb), (2fa ? fb), (fa + 2fb), a nd (fa ? 2fb). the ad7453 is t e s t e d usin g t h e ccif s t anda rd wher e tw o in p u t f r e q u e nc i e s ne a r t h e top e n d of t h e i n put b a nd w i d t h are u s e d . i n th i s ca se , t h e sec o n d - o r d e r t e rm s a r e u s u a ll y d i s t a n ced in f r e q uen c y f r o m t h e o r ig inal si n e wa v e s w h i l e t h e t h ir d-o r der t e r m s a r e us ual l y a t a f r eq uen c y c l os e t o th e in p u t f r eq uen c ies. a s a r e su lt, t h e s e co nd- and t h ird-o r der ter m s ar e sp e c if ie d s e p a r a tely . t h e ca lc u l a t ion o f t h e i n ter m o d u l a t io n disto r t i o n is as p e r t h e thd s p e c if ic a t ion w h er e i t is t h e ra t i o o f t h e r m s s u m o f th e in d i v i d u al d i s t o r ti o n p r od uct s t o th e rm s a m p l i t ud e o f t h e s u m o f t h e f u ndam e n t als exp r es s e d i n db . ap erture dela y t h e a m ou n t of t i m e f r om t h e l e a d i n g e d ge of t h e s a m p l i ng clo c k un t i l t h e ad c ac t u a l ly t a k e s t h e s a m p le. aperture jitter the s a m p le-t o- s a m p le va r i a t ion in t h e ef fe c t i v e p o in t i n t i m e a t w h ich t h e ac t u a l s a m p le is t a k e n. full power bandwidth t h e full po w e r ba n d w id th o f a n ad c i s t h e in p u t f r eq ue n c y a t w h ich t h e a m pl i t ude o f t h e r e con s t r uc t e d f u ndam e n t al is r e d u ced b y 0.1 db o r 3 db f o r a f u l l -s cale in p u t. in tegral non l i n earity (inl) the maxi m u m de v i a t ion f r o m a st ra ig h t li n e p a ssin g t h r o ug h th e en d p o i n t s o f th e ad c tra n sf e r fun c ti o n . differe ntial no nlinearity (dn l ) the dif f er ence b e tw e e n t h e m e as ur e d and t h e i d e a l 1 ls b c h a n g e be tw een a n y tw o a d j a cen t cod e s i n t h e a d c . offset error the devia t ion of th e f i rs t co de t r a n si tio n (000... 000 t o 000...001) f r o m t h e ide a l (i.e ., a g nd + 1 ls b) gain error this is t h e de via t io n o f t h e l a s t co de tra n s i tio n (111...110 t o 111...111) f r o m th e ideal (i .e ., vref C 1 ls b), a f t e r th e o f fs et er r o r has b e en ad j u s t e d o u t. track-and - hol d acquisition time the mi nim u m t i me r e q u ir e d for t h e t r ack and h o ld am plif ier to r e ma in i n t r ack m o d e fo r i t s o u t p u t t o r e ach and s e t t le t o w i t h i n 0.5 ls b o f th e a p p l ied in p u t sig n al . power supply rejection ratio (psrr) the ra t i o o f t h e p o w e r in t h e a d c o u t p u t a t f u l l -s cale f r e- qu e n c y , f , t o th e p o w e r o f a 100 mv p-p sin e wa v e a p p l ie d t o t h e ad c v dd su p p l y of f r e q u e nc y f s . th e f r e q ue n c y o f t h is in p u t va r i es f r o m 1 kh z t o 1 m h z. ps rr (db) = 10l og( pf / pf s ) pf is th e p o w e r a t f r eq uen c y f in t h e a d c o u t p u t ; pf s is t h e po w e r a t f r eq u e n c y f s in t h e ad c o u t p ut.
ad7453 r e v. b | pa ge 9 o f 2 0 ad7453Ctypical performance characteristics d e fa u l t c o ndi t i o n s: t a = 25c, f s = 555 ks ps, f sc l k = 10 mh z, v dd = 2.7 v t o 5.25 v , v ref = 2.5 v , unles s o t h e r w is e n o t e d. frequency (khz) 55 10 s i nad (db) 100 277 60 65 70 75 v dd = 5.25v v dd = 2.7v v dd = 3.6v v dd = 4.75v 03155-a - 005 f i g u re 5. sina d v s . a n al og input f r equ e nc y f o r v a ri ous su p p ly v o lt ag es 0 ?20 ?40 ?80 ?60 ? 120 ? 100 ? 140 03155-a - 006 supply ripple frequency (khz) 0 100 200 300 400 500 p s rr ( d b ) 900 1000 v dd = 5v v dd = 3v 600 700 800 100mv p-p sine wave on v dd no decoupling on v dd f i g u r e 6 . p s r r v s . s u pp l y ripp le f r e q ue n c y w i t h o u t s u pp ly de c o u p l i n g frequency (khz) 0 100 200 s nr (db) ?100 ?140 277 ?2 0 0 ?120 ?4 0 ?6 0 ?8 0 8192 point fft f sample = 555ksps f in = 100ksps sinad = 71.7db thd = ? 82db sfdr = ? 83db 03155-a - 007 f i gure 7. d y na mi c p e r f o r m a nce fo r v dd = 5 v code dn l e r ro r ( l s b ) 1.0 0.8 0.6 0.2 0.4 ?0.2 ?0.4 ?0.6 ?0.8 0 ?1.0 0 1024 3072 2048 4096 03155-a - 008 f i g u re 8. t y pic a l d n l f o r t h e a d 74 53 f o r v dd = 5 v code i n l er r o r (l sb ) 1.0 0.8 0.6 0.2 0.4 ?0.2 ?0.4 ?0.6 ?0.8 0 ?1.0 0 1024 3072 2048 4096 03155-a - 009 f i gure 9. t y pic a l in l for the a d 7 4 53 f o r v dd = 5 v codes 0 2046 2047 2 048 2049 2050 2051 27 codes 24 codes 9949 codes 1000 2000 3000 4000 5000 6000 7000 8000 9000 10000 03155-a - 010 f i g u re 10. h i s t og r a m of 1 0 ,0 0 0 conver s i ons of a dc input
ad7453 rev. b | page 10 of 20 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 change in dnl (ls b ) 0123 4 5 v ref (v) 03155-a - 011 positive dnl negative dnl f i gure 1 1 . change in dnl vs . v ref fo r v dd = 5 v ?2 ?1 0 1 2 3 4 5 change in inl (ls b ) 0123 4 5 v ref (v) 03155-a - 012 positive inl negative inl f i gure 1 2 . change in inl vs . v ref for v dd = 5 v 6 7 8 9 10 11 12 e ffe ctiv e numbe r of bits 2 13 04 v ref (v) 03155-a - 013 5 v dd = 3v v dd = 5v f i g u re 13. e n ob v s . v ref for v dd = 3 v a n d 5 v
ad7453 rev. b | page 11 of 20 circuit i n formation the ad7453 is a 12-b i t, lo w p o w e r , sin g le-s u p pl y , s u cces s i v e a p p r o x im a t ion a n a l og-t o-dig i t a l co n v er t e r (ad c ) wi t h a ps eudo dif f er en t i al a n alog i n p u t. i t o p era t es w i t h a sin g le 2.7 v t o 5.25 v p o w e r s u p p l y a nd is c a p a b l e o f thr o ug h p u t r a t e s u p to 555 ks ps w h en s u p p lie d wi th a 10 mh z sclk. i t r e q u ir es a n e x te r n a l re fe re nc e to b e a p pl i e d to t h e v ref pi n . the ad7453 has a n o n -c hi p dif f er en tial track-and-h o ld a m plif ier , a succ essi v e a p p r o x im a t io n (s ar) a d c, a nd a s e r i a l i n t e rfa c e , h o use d i n a n 8- lead so t - 23 pa c k a g e . t h e seri al c l ock in p u t acces s es da t a f r o m t h e p a r t a nd p r o v ides t h e clo c k s o ur ce f o r th e s u cces siv e a p p r o x ima t ion ad c. th e ad7453 f e a t ur es a p o we r - d o w n opt i on f o r re d u c e d p o we r c o nsu m pt i o n b e t w e e n co n v ersio n s. the p o w e r - do w n fe a t ur e is im ple m e n t e d acr o s s t h e st anda r d s e r i a l i n ter f ace, as de s c r i b e d i n t h e m o des o f o p er a t ion s e c t i o n. converter operation the ad7453 is a s u cces si v e a p p r o x ima t ion ad c bas e d a r o u n d t w o c a p a c i t i v e d a c s . fi g u r e 1 4 a n d fi g u r e 1 5 s h o w s i m p l i f i e d s c h e ma t i c s o f t h e ad c in t h e acq u isi t io n an d c o n v ersio n phas e, r e s p ec ti v e l y . the ad c is co m p r i s e d o f co n t r o l l o g i c, a n sar , a nd tw o ca p a c i t i v e d a cs. i n f i gur e 14 (acq uisi tio n p h as e), sw3 is clos e d an d s w 1 an d s w 2 a r e in p o si t i on a, t h e com p a r a t o r is hel d i n a b a l a nc e d c o nd i t i o n , an d t h e s a m p l i ng c a p a c i tor ar r a y s acq u ir e t h e dif f er en t i a l sig n al on t h e in p u t. v in+ v in? a b sw1 sw3 comparator control logic capacitive dac capacitive dac c s c s v ref sw2 b a 03155-a - 014 f i g u re 14. a d c ac quis it i o n p h as e w h en t h e ad c s t a r ts a con v ersio n (f igur e 15), sw3 o p e n s an d sw1 and sw2 m o v e t o p o si tion b , c a usin g the co m p a r a t o r t o beco m e un bala n c e d . b o th in p u t s a r e d i sco n n e c t ed o n ce t h e co n v ersio n b e g i n s . th e co n t r o l log i c a n d cha r g e r e dis t r i b u t i o n d a cs a r e us e d to add an d sub t r a c t f i xe d am o u n t s o f cha r ge f r o m th e sam p lin g ca p a ci t o r a r ra ys t o b r in g t h e co m p a r a t o r bac k in t o a b a lan c e d con d i t ion. w h en t h e com p a r a t o r is r e bal- a n c e d , t h e con v ersio n is co m p l e t e . th e con t r o l log i c g e n e ra t e s t h e ad c s o u t p u t co de . the o u t p u t i m p e dan c es o f t h e s o ur ces dr i v i n g t h e v in+ a nd v inC pi ns m u st b e m a tc he d ; ot he r w i s e t h e tw o in p u ts h a v e dif f er en t s e t t ling t i m e s, r e su l t i n g in er r o rs. v in+ v in? a b sw1 sw3 control logic capacitive dac capacitive dac c s c s v ref sw2 b a 03155-a - 015 comparator f i g u re 15. a d c co nvers i on p h as e adc tra n s f er func ti on the o u t p u t co din g f o r th e ad74 53 is s t ra ig h t (na t ural) b i na r y . the desig n e d c o de tra n si t i o n s o c c u r a t s u cces s i v e ls b va l u es (i .e ., 1 ls b , 2 ls b , a nd s o o n ). th e l s b size is v ref /4096. th e ideal tra n sf er c h a r ac t e r i s t ic o f th e ad7453 is sh o w n in f i gur e 16. 000...00 0v adc co de analog input 111...11 000...01 111...00 011...11 1lsb v ref ? 1lsb 1lsb = v ref /4096 111...10 000...10 03155-a - 016 f i gur e 1 6 . idea l t r ansfe r char act e r i stic
ad7453 rev. b | page 12 of 20 typical connection diagram f i gur e 17 s h o w s a typ i cal co nn e c tio n dia g ram f o r th e ad7453. i n t h is s e t u p , t h e gnd p i n is conn e c te d to t h e ana l o g g r o u n d plan e o f t h e sys t em. th e v ref p i n is co nn ec ted to th e ad780, a 2.5 v deco u p le d r e f e r e n c e s o ur c e . the sig n al s o ur ce is co nnec- te d to t h e v in+ ana l og in p u t v i a a uni t y ga in b u f f er . a dc vol t a g e is co nne c t e d to t h e v in C p i n t o p r o v ide a ps eudo g r o u n d fo r t h e v in+ in p u t . th e v dd p i n sh o u l d b e d e co u p le d to a g nd w i t h a 10 f ta n t al u m ca p a c i t o r in p a r a l l e l wi th a 0.1 f cera mic c a p a c i tor . t h e re f e re nc e pi n s h ou l d b e d e c o up l e d to a g n d w i t h a c a p a ci t o r o f a t leas t 0.1 f . the co n v ersion r e su l t is o u t p u t in a 16-b i t w o r d wi t h f o ur le adin g zer o s f o llo w e d b y th e ms b o f the 12-b i t r e s u l t . v in+ v in? v dd sclk sdata cs gnd v ref serial interface +2.7v to +5.25v supply 2.5v ad780 ad7453 v ref p-to-p dc input voltage c/ p 03155-a-017 0.1 f 10 f 0.1 f f i g u re 17. t y pic a l conne c t io n d i ag r a m the analog inpu t the ad7453 has a ps eudo dif f er en tial a n alog in p u t. th e v in+ in p u t is co u p led t o th e sig n al s o ur ce a nd m u st ha v e an am p l i- tu d e of v ref p-p t o mak e us e o f t h e f u l l d y na mi c ra n g e o f t h e p a r t . a dc in p u t is a p plie d t o v in C . th e v o l t a g e a p plie d t o t h is i n put prov i d e s a n of f s e t f r om g r ou nd or a p s e u d o g r ou nd f o r th e v in + i n p u t. the ma i n b e n e f i t o f ps eudo dif f er en t i a l in p u ts is tha t t h ey s e p a ra t e t h e a n alog in p u t sig n al g r oun d f r o m t h e a d c s g r ou nd, a l l o w i ng d c c o m m o n - m o d e v o lt age s to b e c a nc el l e d. b e c a u s e t h e a d c op e r a t e s f r om a s i ng l e su p p ly , i t is ne c e ss ar y t o le v e l shif t g r oun d -bas e d b i p o la r sig n als t o co m p l y wi th t h e in p u t r e q u ir emen ts. an o p a m p (f o r exa m p l e , th e ad8021) c a n b e co nf igur e d to r e s c a l e a nd le vel shif t a g r o u nd-b a s e d (b i p olar ) si gn al so th a t i t i s co m p a t i b le wi th th e i n p u t ra n g e o f th e ad7453. s e e f i gur e 18. w h en a con v ersio n t a k e s pl ace , t h e ps eudo g r o u nd co r r es p o n d s t o 0 a nd t h e maxim u m analog in p u t co r r es p o nds t o 4096. external v ref (2.5v) r v in+ v in ? ad7453 2.5v 1.25v 0v v ref +1.25v 0v ?1 .25v v in r 3r 0.1 f r 03155-a - 018 f i g u re 18. o p a m p conf ig ur at i o n to l e vel sh if t a b i po l a r i n put sig n al analog input structure f i gur e 19 s h o w s th e e q ui valen t cir c ui t o f th e a n alog in p u t s t r u c- t u r e o f th e ad7 453. th e f o ur dio d es p r o v ide es d p r o t ec tion f o r th e a n alog i n p u t s . c a r e m u s t be tak e n t o e n s u r e th a t t h e a n alog in p u t sig n als ne v e r exce e d th e su p p l y ra ils b y m o r e tha n 300 mv . this c a us es th es e dio d es t o become f o r w a r d b i as e d and t o s t a r t co nd uc t i n g i n t o t h e s u b s t r a t e . th es e di o d es can con d u c t u p t o 10 ma wi th o u t ca usin g ir r e v e rsi b le da mag e t o th e p a r t . the c a p a ci t o rs, c1 in f i gur e 19, a r e typ i cal l y 4 pf a n d can b e a t t r ib ut e d p r ima r i l y t o p i n c a p a ci t a n c e . the r e sist o r s a r e lu m p e d c o m p o n e n t s m a d e up of t h e on re s i st a n c e of t h e swi t ch es. th e va l u e o f th es e r e sis t o r s is typ i cal l y a b o u t 100 ?. the c a p a ci t o rs c2 a r e th e ad c s s a m p lin g ca p a ci t o rs, a nd ha v e a typ i cal c a p a ci t a n c e o f 16 pf . f o r a c a p pl i c a t i o ns , re mov i ng h i g h f r e q u e nc y c o m p o n e n t s f r om th e a n alog i n p u t si gn al th r o ugh th e use o f a n rc lo w - pa s s f i l t er o n t h e r e le v a n t a n a l og in p u t p i n s is r e co m m e nde d . i n a p plica - t i o n s w h er e ha r m o n ic dis t o r t i on an d sig n a l -t o- n o is e r a t i o a r e cr i t ica l , t h e a n a l og in p u t sh o u l d b e dr i v e n f r o m a lo w im p e d- a n c e s o ur ce . l a rge s o ur ce im p e dan c es sig n if ican t l y a f fe c t t h e a c p e r f o r ma n c e o f t h e ad c, w h ich ma y ne ces s i t a t e t h e us e o f a n in p u t b u f f er a m plif ier . th e ch o i ce o f t h e o p am p is a f u n c t i on of t h e p a r t ic u l a r a p plica t io n. c1 c2 r1 d d c1 c2 r1 d d v dd v dd 03155-a - 019 v in+ v in? f i g u re 19. equiv a le nt a n al og input c i rcuit . convers i on p h as e switc h es o p e n ; t r ack phas e sw itc h es cl os ed
ad7453 rev. b | page 13 of 20 w h en n o am pli f ier is us e d t o dr i v e t h e a n alog in p u t, t h e s o ur ce im p e dan c e sh ou ld be limi t e d to lo w val u es. the maxim u m s o ur ce im p e dance dep e n d s on t h e am o u n t o f tot a l ha r m o n ic d i stor t i on ( t h d ) t h a t c a n b e t o l e r a te d. t h e t h d i n c r e a s e s a s t h e s o ur ce i m p e dan c e i n cr e a s e s a nd p e r f o r ma n c e deg r ades. f i g u re 2 0 show s a g r a p h of t h e t h d ve r s u s an a l o g i n put s i g n a l f r e q uen c y fo r dif f er en t s o ur ce im p e dances. input frequency (khz) ? 100 10 thd (db) 100 277 ?80 ?50 ?40 0 200 ? ?10 ?20 ?30 ?60 ?70 ?90 10 ? 62 ? 100 ? 03155-a - 020 f i g u re 20. th d v s . a n al og input f r equ e nc y f o r v a ri ous s o ur c e impeda nc es f i g u re 2 1 show s a g r a p h of t h d ve r s u s an a l o g i n put f r e q u e nc y for v a r i ou s su p p ly vol t age s w h i l e s a m p l i ng a t 5 5 5 ks p s wi t h an sclk o f 10 mh z. i n this cas e , t h e s o ur ce im p e dan c e is 10 ?. ?90 10 thd (dbs ) t a = 25c v dd = 2.7v v dd = 3.6v v dd = 4.75v v dd = 5.25v 100 277 ?85 ?80 ?75 ?70 ?65 ?60 ?55 ?50 input frequency (khz) 03155-a - 021 f i g u re 21. th d v s . a n al og input f r equ e nc y f o r v a ri ous su p p ly v o lt ag es digi tal in p u ts the dig i tal in p u ts a p p l ie d t o t h e ad7453 a r e n o t limi t e d b y t h e m a xi m u m ra tin g s th a t li mi t t h e a n alog i n p u t s . i n s t ead , th e dig i t a l in p u ts a pplie d , i . e., cs a nd s c lk, can go to 7 v a nd a r e not re st r i c t e d by t h e v dd + 0.3 v limi ts as on th e analog in p u t. the ma i n ad van t a g e o f t h e i n pu ts n o t b e in g r e s t r i c t e d t o t h e v dd + 0 . 3 v l i m i t is t h a t p o we r su p p ly s e qu e n c i ng issu e s are av o i d e d . if cs o r sclk a r e a p p l ie d b e f o r e v dd , t h er e is n o r i s k o f la t c h-u p as t h er e w o u l d be on the a n alog in p u ts if a sig n al g r ea t e r tha n 0.3 v w e r e a p p l ied p r io r t o v dd . reference a n e x te r n a l s o u r c e i s re qu i r e d t o supp ly t h e re f e re nc e to t h e ad7453. this ref e r e n c e in p u t c a n ra n g e f r o m 1 00 mv t o v dd . the s p ecif ied r e f e r e n c e is 2.5 v f o r th e 2.7 v t o 5.25 v p o w e r su p p ly r a nge. t h e re fe re nc e i n pu t cho s e n for an a p pl ic a t ion s h o u ld n e v e r be gr ea t e r tha n t h e p o w e r s u p p l y . er r o r s in th e r e f e r e n c e s o ur c e r e s u l t in gain er r o rs in th e ad7453 tra n sf er f u n c tion. a c a p a ci t o r o f a t leas t 0.1 f s h o u ld b e p l ace d o n t h e v ref p i n. s u i t ab le r e f e r e n c e s o urces f o r th e ad7 453 in c l ude the ad780 an d t h e ad r421. f i gur e 22 s h o w s a typ i cal co nn ec tion d i a g ra m f o r the v ref pi n . 1 ad780 nc 8 2 v in nc 7 3 gnd 6 4 temp 5 opsel trim v out ad7453* v ref 2.5v nc v dd nc v dd nc = no connect 10nf 0.1 f 0.1 f 0.1 f 03155-a - 022 *additional pins omitted for clarity f i g u re 22. t y pic a l v ref c o nnec t ion d i agr a m for v dd = 5 v serial interface f i gur e 2 sh o w s a det a i l e d t i ming di a g r a m o f t h e s e r i a l i n ter f ac e o f th e ad7453. the s e r i al c l o c k p r o v ides the con v ersio n c l o c k a n d co n t r o ls th e tra n sf e r o f d a ta f r o m th e de v i ce d u ri n g co n v ersio n . cs ini t ia t e s t h e con v ersio n p r o c es s and f r a m es t h e da ta tra n sf e r . t h e fallin g ed ge o f cs p u ts t h e t r ack-and- h o ld in t o h o ld m o de a nd ta k e s t h e b u s o u t o f thr e e-s t a t e . th e analog in p u t is s a m p le d an d t h e con v e r sio n is ini t i a t e d a t t h is p o in t. the con v ersio n r e q u ir es 16 scl k c y cles t o co m p let e . on ce 13 s c lk f a l l in g edg e s ha ve o c c u r r ed , th e t r ac k-and-h o ld g o es bac k in t o t r ac k mo de on t h e n e xt sc lk r i sin g edg e , as s h own a t p o in t b in f i gur e 2. o n the 16th sc l k fal l in g e d g e , t h e s d a t a lin e go es bac k in t o thr e e-s t a t e . i f th e r i sin g edge o f cs o c c u rs bef o r e 16 sclks ha v e ela p s e d , t h e con v ersio n i s t e r m ina t e d and t h e s d a t a li n e g o es b a ck in to th r e e - s t a t e . the con v ersio n r e s u l t f r o m th e ad7453 is p r o v ided on t h e s d a t a o u t p ut as a s e r i a l d a t a st r e a m . t h e b i ts a r e clo c k e d o u t o n the fal l in g e d g e o f th e s c l k in p u t. the da ta s t r e am o f th e ad7453 co n s is ts o f f o ur leadin g zer o s, f o l l o w ed b y 12 b i ts o f c o n v e r s i on d a t a , prov i d e d m s b f i r s t . t h e output c o d i ng i s s t ra igh t (na t ura l ) b i na r y .
ad7453 rev. b | page 14 of 20 timing example 1 sixt e e n s e r i al cl o c k c y cles a r e r e q u ir e d t o p e r f o r m a con v ersio n a nd t o access da ta f r o m the ad7453. cs go in g lo w p r o v ides t h e f i rst le adin g zero t o b e r e ad in b y t h e micr o c on t r ol ler o r ds p . the r e ma in in g d a t a is t h e n clo c k e d o u t on t h e subs e q ue n t sclk fal l in g edg e s, beg i nnin g wi t h t h e s e co nd leadin g zer o . th us t h e f i rs t fa l l in g clo c k e d ge o n t h e s e r i al clo c k p r o v ides t h e s e con d le adin g zer o . th e f i nal b i t in the da t a tran sf er is valid o n th e 16 th f a l l i n g ed g e , h a v i n g be e n c l oc k e d o u t o n t h e p r ev i o u s (15 th ) fal l in g e d g e . on ce t h e con v ersio n is com p let e an d t h e da t a has b e en acces s ed a f t e r t h e 16 clo c k c y c l es, i t is im p o r t an t t o e n su re t h at , b e f o re t h e ne x t c o n v e r sio n is ini t i a te d , e n o u g h t i me is lef t t o m e e t t h e acq u isi t ion and q u iet t i m e sp e c if ica t ion s . s e e ti m i n g e x a m p l e 1 . ha v i n g f sc l k = 10 mh z and a t h r o ug h p u t ra t e o f 555 ks ps g i ves a c y cle t i m e o f 1/ th r o u g h p u t = 1/555,000 = 1.8 s a c y cle co n s is ts o f t 2 + 12.5(1/ f sclk ) + t ac q = 1.8 s ther efo r e if t 2 = 10 n s , 10 n s + 12.5(1/10 mh z) + t ac q = 1.8 s t ac q = 540 n s this 540 n s s a tisf ies th e r e q u ir em en t o f 290 n s f o r t ac q . f r o m f i gur e 23, t ac q co m p r i s e s i n a p plic a t io n s wi t h a slo w er sclk, i t ma y b e p o ssi b le t o r e a d in da ta on each sc lk r i sin g edg e , i. e . , th e f i rs t r i sing edg e o f scl k af te r t h e cs fa l l in g e d ge w o u l d h a ve t h e le a d in g ze r o p r o v ide d , a nd t h e 15 th sc lk edge w o u l d ha v e d b 0 p r o v ided . 2.5(1/ f sclk ) + t 8 + t qu i e t w h er e t 8 = 35 n s . this al lo ws a val u e o f 255 n s f o r t qu i e t , sa ti s f yi n g t h e mi n i m u m r e q u i r em en t o f 60 n s . t 2 t 8 t 6 t 5 t convert cs sclk 12 3 4 5 1 3 1 4 1 5 1 6 03155-a - 023 12.5(1/f sclk ) t acquisition 1/throughput t quiet 10ns f i gure 23. s e ri al inter f ace ti ming e x a m pl e
ad7453 rev. b | page 15 of 20 modes of operation the m o de o f o p era t io n o f t h e ad7453 is s e lec t e d b y co n t r o l l in g t h e log i c s t a t e of t h e cs sig n al d u r i n g a con v ersion. th er e a r e tw o p o ssib le mo des o f o p er a t ion, n o r m a l m o d e a nd p o w e r - do wn m o de. t h e p o in t a t w h i c h cs is p u l l ed hig h a f t e r th e co n v ersio n has been ini t ia t e d det e r m in es w h et h e r t h e ad7453 en t e r s po w e r - do w n m o de . s i m i la r l y , i f alr e a d y i n po w e r - d o w n , cs co n t r o ls w h et her t h e de vice r e t u r n s t o n o r m al o p era t ion o r r e ma in s i n p o wer - do w n . th es e m o de s o f o p era t io n a r e desig n e d to prov i d e f l e x ibl e p o we r m a n a ge me n t opt i ons . t h e s e opt i o n s ca n b e ch o s e n to o p t i mi ze t h e p o w e r dissi p a t i o n/ t h r o ug h p u t ra t e ra t i o f o r d i f f er in g a p p l ica t io n r e q u ir em en ts. normal m o de this m o d e is in t e nde d fo r fast e s t t h r o ug h p ut ra t e p e r f o r ma n c e . the us er do es no t ha v e t o w o r r y a b o u t an y p o w e r - u p t i m e s w i t h th e ad7453 r e ma inin g f u l l y p o w e r e d u p al l the tim e . f i gur e 2 4 s h o w s t h e g e n e r a l dia g ra m o f t h e o p era t ion o f th e ad7453 in t h is m o de . t h e co n v ersio n is in i t i a te d on t h e fa l l in g e d ge o f cs , a s d e sc ri bed i n th e s e ri al i n t e rfa c e secti o n . t o en s u r e th a t th e pa r t r e m a i n s full y po w e r e d u p , cs m u s t r e ma in lo w un til a t leas t 10 scl k f a l l in g edg e s ha ve e l a p s e d a f t e r t h e fal l in g edge of cs . if cs i s b r o u gh t h i gh a n y tim e a f t e r th e 1 0 t h s c lk f a ll i n g ed g e but b e f o re t h e 1 6 th s c l k f a ll in g ed g e , th e pa r t r e m a i n s po w e r e d u p b u t t h e con v ersio n is t e r m ina t e d and s d a t a g o es b a ck in to thr e e-s t a t e . s i xteen s e r i al c l o c k c y c l es a r e r e q u ir ed t o com p let e t h e con v ersio n a nd access t h e c o m p let e con v ersio n r e s u l t . cs ma y idle hig h u n til t h e n e xt con v ersio n , o r ma y idle lo w un til so m e tim e p r i o r t o th e n e xt co n v e r si o n . o n ce a da ta tra n sf e r i s c o m p l e t e , i . e . , w h e n s d a t a h a s r e t u r n e d t o t h r e e - s t a t e , a n o t h e r co n v ersio n can be ini t ia t e d a f t e r th e q u iet tim e , t qu iet , h a s el a p s e d b y ag ai n b r i n g i ng cs lo w . 11 0 cs sclk sd a t a 16 4 leading zeros + conversion result 03155-a - 024 f i g u re 24. no r m a l m o de o p er at io n power-down mode this m o d e is in t e nde d fo r us e in a p pli c a t io n s w h er e slo w er t h rou g h p ut r a te s are re qu i r e d t he a d c i s p o we re d d o w n b e t w e e n e a c h c o n v e r s i on , or a s e r i e s of c o n v e r s i ons m a y b e p e r f o r m e d a t a hig h t h r o ug h p ut r a te and t h e a d c is t h en p o w e r e d do w n fo r a r e la t i vely lon g d u r a t i o n b e t w e e n t h es e b u rs ts o f s e veral co n v ersio n s. w h en the ad745 3 is in p o w e r - do wn m o de, a l l a n a l o g cir c ui t r y is p o w e r e d do w n . f o r t h e ad7453 t o en t e r p o w e r - do wn m o de , the con v ersio n p r o c es s m u st b e i n te r r upte d b y b r i n g i ng cs hig h an y w h e re a f t e r the s e con d fal l in g e d g e o f sclk and b e f o r e th e 10 th fallin g edg e o f sclk, as sh own in f i gur e 25. on ce cs h a s been b r o u gh t hi gh in th i s w i n d o w o f s c l k s , th e p a r t en t e rs p o w e r - do w n , t h e con v ersio n t h a t w a s ini t ia te d b y th e fal l in g edge o f cs is t e r m ina t e d , a nd sd a t a go es b a ck i n t o th r e e - s t a t e . th e ti m e f r o m th e ri si n g ed g e o f cs to sd a t a t h r e e-s t a t e ena b le d is ne v e r g r e a t e r t h a n t 8 (se e t h e t i min g s p e c if ic a t io n s ). i f cs i s b r o u gh t h i gh be f o r e th e s e c o n d s c lk fa l l in g e d ge, t h e p a r t r e ma in s in n o r m a l m o de and do es n o t p o w e r do wn. t h is a v o i ds a c cid e n t a l p o w e r - do w n d u e to g l i t ches on t h e cs lin e . t o exi t this mo de o f o p era t ion a nd p o w e r u p th e ad7453 a g a i n, a d u m m y c o n v e r s i on i s p e r f or me d. o n t h e f a l l i n g e d ge of cs , th e de vice b e g i n s t o p o w e r u p , a nd co n t in ues to p o w e r u p as lo n g as cs is h e ld l o w un til a f t e r t h e fal l in g e d ge o f th e 10 th sclk. t h e de vi ce is f u l l y p o w e r e d u p a f ter 1 s has el a p s e d and , a s s h ow n i n fi g u re 2 6 , v a l i d d a t a re su lt s f r om t h e ne x t co n v ersio n . if cs i s b r o u gh t h i gh be f o r e th e 1 0 th fal l in g edge o f sclk, the ad7453 a g ain go es bac k in t o p o w e r - do wn. this a v o i ds acciden t al p o w e r - u p d u e t o g l i t ch es on t h e cs lin e o r a n inad v e r t e n t b u rst o f eig h t s c l k c y cles w h i l e cs is lo w . s o al th o u g h th e de v i ce ma y be gin t o po w e r u p o n th e fallin g ed ge of cs , i t ag ai n p o we rs d o w n on t h e r i s i ng e d ge of cs as lo n g as i t o c c u rs b e f o r e th e 10 th s c lk f a l l in g edge . 1 10 cs sclk sdata three-state 2 03155-a - 025 f i gure 25. enter i ng p o w e r - d o wn mod e
ad7453 rev. b | page 16 of 20 power-up time the p o w e r - u p t i me o f th e ad7 453 is typ i cal l y 1 s, whic h m e an s tha t wi t h a n y f r eq uen c y o f sclk u p t o 1 0 mh z, on e d u mm y c y cle is al wa ys s u f f i cien t t o al lo w t h e de vice t o p o w e r u p . on c e t h e d u mm y c y cle is co m p let e , t h e ad c is f u l l y p o w e r e d u p an d t h e i n p u t sig n al is acq u ir e d p r op erl y . the q u iet ti m e , t qu iet , m u st st i l l b e a l l o we d f r om t h e p o i n t a t w h ich t h e b u s g o es b a ck i n t o t h r e e- s t a t e af t e r t h e d u mm y co n v ersio n t o th e n e xt falli n g ed g e o f cs . w h en r u nnin g a t t h e maxim u m thr o ug h p u t ra t e o f 555 ks ps, th e ad7453 p o w e rs u p a nd acq u ir es a sig n al wi thin 0.5 ls b in o n e du m m y c y c l e . wh e n p o w e r i n g up f r o m p o w e r - d o w n m o d e wi t h a d u m m y c y cle, as in f i gur e 26, t h e t r ack a nd- h o ld , w h ich was i n h o l d m o de w h i l e t h e p a r t was p o w e r e d d o wn, r e t u r n s t o t r ack m o de a f t e r t h e f i rs t scl k e d g e t h e p a r t r e cei v es a f t e r t h e fallin g edg e o f cs . this is sh o w n a s p o in t a i n f i g u r e 26. al th o u g h a t a n y sclk f r eq uen c y o n e d u mm y c y c l e i s s u f f i ci en t to p o w e r u p t h e de vice and ac quir e v in , i t d o e s not ne c e ss ar i l y m e an t h a t a f u l l d u m m y c y cle o f 16 sclks m u st a l wa y s ela p s e to p o w e r u p t h e de vice and ac quir e v in f u l l y ; 1 s is s u f f i cien t to p o w e r u p t h e de vice and ac q u ir e t h e in pu t sig n al . f o r exa m ple , if a 5 mhz scl k f r e q uen c y is a pplie d t o t h e ad c, th e c y c l e tim e is 3.2 s (i .e ., 1/(5 mh z) 16). i n o n e d u mm y c y cle, 3.2 s, t h e p a r t is p o w e r e d u p a nd v in is a c q u ir e d f u l l y . h o w e v e r a f t e r 1 s wi th a 5 m h z sclk, onl y f i v e sclk c y c l es ha ve e l a p s e d. a t t h i s st ag e, t h e a d c i s f u l l y p o we re d up and t h e sig n a l acq u ir e d . s o in t h is cas e , cs c a n be b r o u gh t h i gh a f t e r th e 10 th s c l k f a l l i n g e d ge a n d b r ou g h t l o w ag ai n af te r a t i me, t qu iet , to i n i t i a te t h e c o n v e r s i on. w h en p o w e r s u p p lies a r e f i rs t a p p l ied t o t h e ad7453, th e ad c ma y ei t h er p o wer u p in t h e p o w e r - do w n m o de o r n o r m al m o de . b e ca us e o f this, i t is bes t t o al lo w a d u mm y c y c l e t o e l a p s e t o e n su re t h at t h e p a r t i s f u l l y p o we re d up b e f o re a tte mpt i ng a valid con v ersion. l i k e wis e , if t h e us er wan t s t h e p a r t t o p o w e r u p in p o w e r - do w n m o de, t h e d u mm y c y cle ma y b e us e d to en s u r e t h e de v i ce is in p o w e r - do wn m o de b y exe c u t in g a c y cle s u c h as tha t sh o w n in f i gur e 25. on ce s u p p lies a r e a p p l ie d t o th e ad7453, t h e p o w e r - u p time is th e s a m e as tha t w h en po w e ri n g u p f r o m po w e r - d o w n m o de . i t tak e s a p p r o x i m a t e l y 1 s t o p o w e r u p f u l l y if th e p a r t p o w e rs u p in n o r m al m o de . i t i s not ne c e ss ar y to w a i t 1 s b e f o re e x e c ut i n g a d u m m y c y cl e to en s u r e t h e desire d m o de o f o p e r a t io n. i n s t e a d , t h e d u mm y c y cle ca n o c cur d i r e ctl y a f t e r p o w e r is s u p p lied t o the ad c. i f the f i rst va lid con v e r sio n is t h e n p e r f o r m e d dir e c t ly a f ter t h e d u mm y con v ersio n , ca r e m u s t b e t a k e n t o en s u re t h a t ade q ua t e acq u isi t ion t i m e has b e en a l lo w e d . a s m e n t ion e d e a rlier , w h e n p o w e r i n g u p f r o m t h e p o w e r - do w n m o de , th e pa r t r e t u rn s t o tra c k m o de u p o n t h e f i r s t sc l k e d g e a p plie d a f t e r t h e fa l l in g e d ge o f cs . h o w e v e r , w h e n t h e a d c p o w e rs u p ini t ia l l y a f t e r su p p lies a r e a p plie d , t h e t r ack-and- h o l d is a l r e ad y in t r a c k m o de . t h is m e an s (assu mi n g o n e has t h e faci li ty t o m o ni to r t h e a d c su pply c u rr en t) t h a t if t h e ad c p o w e rs u p in t h e desir e d m o d e o f o p er a t io n and t h us a d u m m y c y cl e is not re qu ire d to chang e t h e mo de, t h e n a d u m m y c y cl e is n o t r e q u ir e d t o place t h e t r ack- a nd- h o ld i n t o t r ack. cs sclk sdata 1 10 1 6 1 1 0 1 6 a this part is fully powered up with v in fully acquired part begins to power up invalid data valid data t power-up 03155-a - 026 f i g u re 26. e x it ing p o wer - d o wn m o de
ad7453 rev. b | page 17 of 20 power vs. throughput rate by usin g t h e p o w e r - do w n m o de o n t h e ad745 3 w h en n o t con- v e r t in g, t h e a v er a g e p o w e r co n s um p t ion o f t h e ad c de cr e a s e s a t l o we r t h rou g h p ut r a te s . f i g u re 2 7 show s how , a s t h e t h rou g h - p u t ra te is r e d u c e d , the device r e ma in s in i t s p o w e r - do wn s t a t e lo n g er a nd the a v era g e p o w e r con s um p t io n r e d u ces acco r d in g l y . f o r exa m p l e , if th e ad7453 is op era t e d in con t in uo us s a m p ling m o de wi t h a thro ug h p u t r a t e o f 100 ks ps and a 10 mh z sclk, a nd t h e d e vice i s place d in t h e p o w e r - do w n mo de b e twe e n con- v e rsio n s , t h en t h e p o w e r co n s u m p t ion is ca lc u l a t e d as fol l o w s: p o w e r di ss ip a t i o n du r i n g n o r m al op e r a t i o n = 7.25 mw max ( fo r v dd = 5 v). i f th e p o w e r - u p time is on e d u mm y c y c l e (1.06 s if cs is b r o u gh t hi gh a f t e r th e 1 0 th scl k fal l in g e d g e i n t h e c y cle a nd t h e n b r o u g h t lo w a f t e r t h e q u ie t t i m e ) an d t h e r e ma inin g co n v ersio n t i m e is a n o t h e r c y c l e (1.6 s), th en t h e ad7453 ca n be s a id t o dis s i p a t e 7.25 mw f o r 2.66 s ? du r i n g e a c h co n v ersio n c y c l e . i f th e thr o ug h p u t ra t e = 100 ks ps, th en t h e c y cle time = 10 s a nd t h e a v era g e p o w e r dis s i p a t e d d u r i n g e a ch c y cle is (2.66/10) 7.25 mw = 1.92 mw f o r th e sa m e sce n a r i o , i f v dd = 3 v , t h e p o w e r d i ssi p a t ion d u r i ng n o r m al o p er a t io n is 3.3 mw max. th e ad7453 ca n n o w be s a id t o dis s i p a t e 3.3 mw f o r 2.66 s ? d u r i ng e a ch c o n v ers i on c y cl e. the a v er a g e p o w e r dis s i p a t e d d u r i n g e a ch c y cle wi t h a thr o ug h p u t ra t e o f 100 ks ps is th er ef o r e (2.66/10) 3.3 mw = 0.88 mw this is h o w t h e p o w e r n u m b ers in f i gur e 27 a r e ca lc u l a t e d . throughput (ksps) 100 0 350 p o we r (mw) 0.01 50 100 150 200 250 300 0.1 1 10 v dd = 5v v dd = 3v 03155-a - 027 f i gure 27. p o wer v s . thro ughput r a te f o r p o wer - d o w n m o de ? this f i gure ass u mes a v e ry s h ort time t o en t e r power- d o w n m o de. th i s incre a s e s as the burs t of cl o c ks us ed to e nte r po we r do wn mo d e is i n crea sed. f o r thr o ug h p u t ra t e s abo v e 320 ks ps, the s e r i al c l o c k f r eq uen c y shou l d b e re d u c e d f o r opt i m u m p o we r p e r f or manc e. microproc e ssor and dsp inter f acing the s e r i al in ter f ace o n t h e ad7 453 al lo ws th e p a r t t o be con- n e c t e d dir e c t l y to a ra n g e o f dif f er en t micr o p r o c e s s o r s. this s e c t io n exp l ain s h o w t o in t e r f ac e th e ad7453 wi th s o m e o f t h e m o r e co m m on micr o c o n t r ol ler and ds p s e r i a l in ter f ace proto c o l s . ad7453 to adsp-21xx the a d s p -21xx fa mi l y o f ds p s a r e in t e r f ace d dir e c t l y t o t h e ad7453 wi t h o u t a n y g l ue log i c r e q u ir ed . the s p or t con t r o l r e g i ster sh ou ld b e s e t u p as fol l o w s: t f sw = rfsw = 1 al t e r n a t e f r amin g invrfs = inv t fs = 1 a c ti v e l o w f r am e sig n al d t yp e = 00 rig h t j u s t if y da ta s l en = 1111 16-b i t d a t a -w or ds isclk = 1 i n t e rn al s e ri al cloc k t f sr = r f sr = 1 fr ame e v e r y w o rd irfs = 0 itfs = 1 t o im p l em en t p o w e r - do wn m o de , s l en s h o u l d b e s e t t o 1001 to issu e an 8 - bi t s c l k b u rst. the co nn ec tion dia g ra m is sh own in f i gur e 28. the ads p -21xx h a s th e t f s a n d r f s o f th e s p o r t ti e d t o g e t h e r , w i t h t f s set as a n o u t p ut and rfs s e t as a n i n p u t. t h e dsp o p era t es in a l ter n a t e f r a m ing m o de and t h e s p or t con t r o l r e g i ster is s e t up a s d e s c r i b e d. t h e f r am e s y nc h r on i z a t i o n s i g n a l ge ne r a te d o n th e t f s i s ti e d t o cs , a n d , a s wi th all si gn al p r ocessi n g a p p l ica- t i o n s, e q uidi st an t s a m p lin g is ne cess a r y . h o w e v e r , in t h is exa m ple , t h e t i m e r i n t e r r u p t is us e d t o co n t r o l t h e s a m p lin g ra te of t h e a d c , a n d, u n d e r c e r t ai n c o nd i t i o ns , e q u i d i st a n t s a m p l i n g ma y n o t b e achi e v e d . ad7453* adsp-21xx* sclk dr rfs tfs sclk sdata cs 03155-a - 028 *additional pins removed for clarity f i g u re 28. inte r f a c i n g to t h e a d s p - 21x x
ad7453 rev. b | page 18 of 20 the t i m e r r e g i s t ers, fo r e x a m ple , a r e lo ade d wi t h a val u e t h a t p r o v ides a n in te r r u p t a t t h e r e quir e d s a m p le in ter v a l . w h e n a n in t e r r u p t is r e ce i v e d , a v a l u e is t r a n smi t t e d wi t h tfs/dt (ad c c o n t ro l word ) . t h e t f s i s u s e d to c o n t ro l t h e r f s an d t h u s t h e re a d i n g of d a t a . t h e f r e q u e nc y of t h e s e r i a l cl o c k i s s e t i n t h e sclkd i v r e g i st er . w h e n t h e ins t r u c t io n t o t r a n smi t w i t h tfs is g i v e n, (i .e ., a x 0 = t x 0), t h e s t a t e o f t h e s c l k is che c k e d . th e ds p wai t s u n t i l t h e sc lk ha s go n e h i g h , lo w , and hig h a g a i n be f o r e tra n sm i ssi o n s t a r t s . i f th e tim e r a n d scl k v a l u e s a r e c h ose n s u c h tha t th e i n s t r u cti o n t o tra n sm i t o c cur s o n o r n e a r th e ri si n g ed ge o f sc l k , th en t h e da ta m a y be tra n sm i t t e d o r i t ma y wai t un t i l t h e n e x t clo c k e d ge. f o r exa m p l e , th e ads p -2111 has a mas t er c l o c k f r eq uen c y o f 16 mh z. i f t h e sclkd i v r e g i st er is lo ade d wi t h t h e val u e 3, a n sclk o f 2 mh z is ob ta ined and eig h t mas t er c l o c k p e r i o d s e l a p s e fo r e v er y sclk p e r i o d . i f t h e t i mer r e g i s t ers a r e lo ade d wi t h t h e val u e 8 03, th en 100.5 s c lks o c c u r betw een in t e r r u p ts and su bs e q u e n t ly b e twe e n t r ans m i t i n st r u c t ions . this s i t u a t ion r e su l t s in n o n e quidist a n t s a m p li n g as t h e t r a n s m i t i n st r u c t io n is o c c u r r i n g o n a n sclk e d g e . i f th e n u m b er o f sclks betw een in t e r r u p ts is a w h ole in t e g e r f i g u r e o f n, eq uidis t a n t s a m p lin g is i m p l em en t e d b y th e ds p . ad7453 to tms320c5x/c5 4 x the s e r i al in ter f ace o n t h e t m s 320c5x/c54x us es a co n t in uo u s s e r i al c l o c k and f r a m e sy n c hr o n iza t io n sig n als t o syn c hr o n ize t h e da t a t r an sfer o p era t io n s w i t h p e r i ph eral de vices li k e t h e ad7453. th e cs in p u t a l lo ws e a s y in t e r f acin g b e tw e e n t h e t m s320c5x/c54x a n d t h e ad7453 wi t h o u t an y g l ue log i c r e q u ir ed . th e s e r i al p o r t o f th e t m s320c5x/c54x is s e t u p t o o p era t e in b u rst m o d e wi t h in t e r n a l clkx (tx s e r i a l clo c k) an d fsx (t x f r a m e syn c ). th e s e r i al p o r t co n t r o l r e gis t er (s pc) m u st ha v e t h e f o llo w in g set u p: fo = 0, fs m = 1, m c m = 1 a nd t x m = 1. th e fo r m a t b i t, fo , ma y b e s e t t o 1 t o s e t t h e w o r d len g t h to eig h t b i ts i n o r der t o im ple m en t t h e p o w e r - do w n m o de on t h e ad7453. th e c o nn ec t i o n dia g r a m is sh o w n in f i gur e 29. f o r sig n a l p r o c essing a p plic a t ion s , i t is im p e r a t i ve t h a t t h e f r am e syn c hr o n iza t ion sig n al f r o m th e t m s320c5x/c54x p r o v ide eq ui d i s t a n t sa m p l i n g . ad7453* tms320c5x/ c54x* clkx dr fsx fsr sclk sdata cs clkr 03155-a - 029 *additional pins removed for clarity f i g u re 29. inte r f a c i n g to t h e tm s 3 2 0 c 5 x / c5 4x ad7453 to ds p56xxx the co nn ec tion dia g ra m in f i g u r e 30 s h o w s h o w the ad7453 c a n b e c o n n e c te d to t h e s s i ( s y n ch ronou s s e r i a l i n te r f a c e ) of th e ds p56xxx fa m i l y o f ds p s f r o m m o t o r o la . t h e ss i is op e r a t e d i n s y n c h r onou s mo d e ( s y n bit i n c r b = 1 ) w i t h i n te r n a l ly ge ne r a te d 1 - b i t cl o c k p e r i o d f r ame s y nc for b o t h tx a nd rx (bi t f s l 1 = 1 a n d bi t f s l0 = 0 in crb). s e t t h e w o r d len g th t o 16 b y s e t t in g b i ts wl 1 = 1 a n d wl0 = 0 in cra. t o im p l em en t t h e p o w e r - do wn mo de o n t h e ad7 453, th e w o r d len g t h can b e cha n ge d t o eig h t b i ts b y s e t t in g bi ts wl1 = 0 a n d wl0 = 0 in cr a. f o r sig n a l p r o c essin g a p plic a t io n s , i t is i m pe ra ti v e th a t th e f r a m e syn c hr o n i z a t i o n si gna l f r o m th e ds p56xxx p r o v id e eq uid i s t an t s a m p lin g . ad7453* dsp56xxx* sclk srd sr2 sclk sdata cs 03155-a - 030 *additional pins removed for clarity f i g u re 30. inte r f a c i n g to t h e ds p 56x x x
ad7453 rev. b | page 19 of 20 application hints grounding and layout the printed circuit board that houses the ad7453 should be designed so that the analog and digital sections are separated and confined to certain areas of the board. this facilitates the use of ground planes that can be easily separated. a minimum etch technique is generally best for ground planes as it gives the best shielding. digital and analog ground planes should be joined in only one place, and the connection should be a star ground point established as close to the gnd pin on the ad7453 as possible. avoid running digital lines under the device as this couples noise onto the die. the analog ground plane should be allowed to run under the ad7453 to avoid noise coupling. the power supply lines to the ad7453 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. fast switching signals like clocks should be shielded with digital ground to avoid radiating noise to other sections of the board, and clock signals should never run near the analog inputs. avoid crossover of digital and analog signals. traces on opposite sides of the board should run at right angles to each other. this reduces the effects of feedthrough through the board. a microstrip technique is by far the best but is not always possible with a double-sided board. in this technique, the component side of the board is dedicated to ground planes while signals are placed on the solder side. good decoupling is also important. all analog supplies should be decoupled with 10 f tantalum capacitors in parallel with 0.1 f capacitors to gnd. to achieve the best from these decoupling components, they must be placed as close as possible to the device. evaluating the ad7453s performance the evaluation board package includes a fully assembled and tested evaluation board, documentation, and software for controlling the board from a pc via the evaluation board controller. the evaluation board controller can be used in conjunction with the ad7453 evaluation board, as well as many other analog devices evaluation boards ending with the cb designator, to demonstrate/evaluate the ac and dc performance of the ad7453. the software allows the user to perform ac (fast fourier transform) and dc (histogram of codes) tests on the ad7453. for more information, see the ad7453 application note that accompanies the evaluation kit.
ad7453 rev. b | page 20 of 20 outline dimensions 13 5 6 2 8 4 7 2. 9 0 bs c pin 1 1. 6 0 bs c 1. 95 bs c 0. 65 bs c 0. 3 8 0. 2 2 0. 15 m a x 1. 3 0 1. 1 5 0. 9 0 sea t i n g pl a n e 1. 4 5 m a x 0. 22 0. 08 0. 60 0. 45 0. 30 8 4 0 2. 80 b s c compliant to jedec standards mo-178ba f i g u re 31. 8-l e ad s m a l l o u t l i n e t r ans i s t or p a ck ag e [so t - 23] (r t - 8) di me nsio ns sho w n i n mi ll im e t e r s ordering guide model temperature r a nge linearity error (lsb) 1 package descri ption package option branding ad7453art- r ee l7 C40c to +85c 1.5 8-lead sot-23 rt-8 c0c ad7453brt-r2 C40c to +85c 1 8-lead sot-23 rt-8 c09 ad7453brt-re e l 7 C40c to +85c 1 8-lead sot-23 rt-8 c09 eval-ad7453c b 2 evaluation bo ar d eval-control brd2 3 controll er boar d 1 linearity error here re fer s to integral n o nlinearity error. 2 this can be us ed a s a s t and a l o ne e v aluatio n bo ard o r in conjunct i o n with the e v al uatio n bo ard co ntro l le r f o r e v al ua tio n /d e m o n s tration purpose s . 3 th e eva l ua t i on boa r d con t r o lle r i s a c o m p let e un i t a llowi n g a p c t o con t r ol a n d com m u n i ca t e wi t h a ll an a l og d e vi c e s eva l ua t i on boa r ds en di n g i n t h e cb de si gn a t or. for a c o mplete evaluation kit, you will need to or der the adc evaluation boar d, i.e., eval- a d 7453cb, the eval-control brd2, and a 1 2 v ac transf ormer. see the ad7453 application note that a ccompanies the evaluation ki t for mor e infor mation. ? 2004 analo g de vices, inc. all rights reserve d . tra d em arks and registered tra d ema r ks are the prop erty of their respective owners . c03155C0 C 2/04(b)

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